Sequential Logic
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Previous: 'Logic Design, Part 8'
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0:07Recap and set the stage for the day moving on to sequential logic
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0:07Recap and set the stage for the day moving on to sequential logic
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0:07Recap and set the stage for the day moving on to sequential logic
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0:30Review the off-stream bug-fix and optimisation to nonrestoring_binary_divider()
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0:30Review the off-stream bug-fix and optimisation to nonrestoring_binary_divider()
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0:30Review the off-stream bug-fix and optimisation to nonrestoring_binary_divider()
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3:59Briefly note real-number approaches to division, including Newton's method,1 Goldschmidt2 and SRT division3
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3:59Briefly note real-number approaches to division, including Newton's method,1 Goldschmidt2 and SRT division3
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3:59Briefly note real-number approaches to division, including Newton's method,1 Goldschmidt2 and SRT division3
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8:15Moving on from deterministic parallel functional programming to sequencing stateful systems
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8:15Moving on from deterministic parallel functional programming to sequencing stateful systems
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8:15Moving on from deterministic parallel functional programming to sequencing stateful systems
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11:15Stateful systems
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11:15Stateful systems
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11:15Stateful systems
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12:57The basic stateful component: register / flip-flop
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12:57The basic stateful component: register / flip-flop
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12:57The basic stateful component: register / flip-flop
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16:31Understanding our existing RegisterNode
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16:31Understanding our existing RegisterNode
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16:31Understanding our existing RegisterNode
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19:02Comment out the SerialMultiplier module and remove "enable" from the RegisterNode
19:02Comment out the SerialMultiplier module and remove "enable" from the RegisterNode
19:02Comment out the SerialMultiplier module and remove "enable" from the RegisterNode
20:02Check out the code for Example37 in the context of our move to a stateful system
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20:02Check out the code for Example37 in the context of our move to a stateful system
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20:02Check out the code for Example37 in the context of our move to a stateful system
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22:08Spec out a Counter class
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22:08Spec out a Counter class
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22:08Spec out a Counter class
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29:31Spec out simulation of the system every time
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29:31Spec out simulation of the system every time
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29:31Spec out simulation of the system every time
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31:23Understanding the necessity of double-buffering
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31:23Understanding the necessity of double-buffering
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31:23Understanding the necessity of double-buffering
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33:32Set up to implement our stateful system
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33:32Set up to implement our stateful system
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33:32Set up to implement our stateful system
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34:50Begin to implement RegisterNode privately setting and type-checking the "next" property
34:50Begin to implement RegisterNode privately setting and type-checking the "next" property
34:50Begin to implement RegisterNode privately setting and type-checking the "next" property
37:11Run it to see that the RegisterNode type-checking works
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37:11Run it to see that the RegisterNode type-checking works
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37:11Run it to see that the RegisterNode type-checking works
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37:20Enable set_next() in RegisterNode to convert literals to their expected type4
37:20Enable set_next() in RegisterNode to convert literals to their expected type4
37:20Enable set_next() in RegisterNode to convert literals to their expected type4
38:20Run it to see that the type-conversion works
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38:20Run it to see that the type-conversion works
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38:20Run it to see that the type-conversion works
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38:56Define Example38 as a counter
38:56Define Example38 as a counter
38:56Define Example38 as a counter
42:02Check out the graph of our counter
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42:02Check out the graph of our counter
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42:02Check out the graph of our counter
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42:39Introduce make_register() in our Linearizer for its RegisterNode() to use
42:39Introduce make_register() in our Linearizer for its RegisterNode() to use
42:39Introduce make_register() in our Linearizer for its RegisterNode() to use
49:09Test linearizing Example38 to see that the inliner doesn't cannot handle our RegisterNode
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49:09Test linearizing Example38 to see that the inliner doesn't cannot handle our RegisterNode
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49:09Test linearizing Example38 to see that the inliner doesn't cannot handle our RegisterNode
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49:35Introduce RegisterNode() in our Transformer
49:35Introduce RegisterNode() in our Transformer
49:35Introduce RegisterNode() in our Transformer
50:51Check out our linearized Example38
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50:51Check out our linearized Example38
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50:51Check out our linearized Example38
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52:12Change RegisterNode() in the Transformer to set the name and increment the counter inline
52:12Change RegisterNode() in the Transformer to set the name and increment the counter inline
52:12Change RegisterNode() in the Transformer to set the name and increment the counter inline
54:20Check out our linearized Example38 to see t2 computed earlier
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54:20Check out our linearized Example38 to see t2 computed earlier
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54:20Check out our linearized Example38 to see t2 computed earlier
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54:52Enable linearizer() to return the registers to set the next state
54:52Enable linearizer() to return the registers to set the next state
54:52Enable linearizer() to return the registers to set the next state
55:48Check out our linearized Example38 to see the next state
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55:48Check out our linearized Example38 to see the next state
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55:48Check out our linearized Example38 to see the next state
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56:14Implement register reading to pull in the next state
56:14Implement register reading to pull in the next state
56:14Implement register reading to pull in the next state
58:41Try to compile Example38
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58:41Try to compile Example38
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58:41Try to compile Example38
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59:48Add tick() and reset() to the compile_template for compile() to emit
59:48Add tick() and reset() to the compile_template for compile() to emit
59:48Add tick() and reset() to the compile_template for compile() to emit
1:03:49Check out the generated code of Example38, to see that it looks reasonable
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1:03:49Check out the generated code of Example38, to see that it looks reasonable
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1:03:49Check out the generated code of Example38, to see that it looks reasonable
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1:04:57Create a simulation test of our stateful Example38
1:04:57Create a simulation test of our stateful Example38
1:04:57Create a simulation test of our stateful Example38
1:07:24Run the Example38 simulation to see the expected results
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1:07:24Run the Example38 simulation to see the expected results
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1:07:24Run the Example38 simulation to see the expected results
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1:08:30Conveniently interacting with stateful circuits
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1:08:30Conveniently interacting with stateful circuits
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1:08:30Conveniently interacting with stateful circuits
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1:09:39Set up to make iterable instances of Example38
1:09:39Set up to make iterable instances of Example38
1:09:39Set up to make iterable instances of Example38
1:11:39Spec out an __iter__() function for Example38
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1:11:39Spec out an __iter__() function for Example38
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1:11:39Spec out an __iter__() function for Example38
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1:13:00Define SimulatorInstance class
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1:13:00Define SimulatorInstance class
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1:13:00Define SimulatorInstance class
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1:18:28Simulate our stateful instances successfully
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1:18:28Simulate our stateful instances successfully
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1:18:28Simulate our stateful instances successfully
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1:20:03A few words on our iterable instances abstraction
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1:20:03A few words on our iterable instances abstraction
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1:20:03A few words on our iterable instances abstraction
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1:21:33Change our SimulatorInstance to reset on creation
1:21:33Change our SimulatorInstance to reset on creation
1:21:33Change our SimulatorInstance to reset on creation
1:22:20Check the code for Example38
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1:22:20Check the code for Example38
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1:22:20Check the code for Example38
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1:23:39Reflect on our newly synchronous system
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1:23:39Reflect on our newly synchronous system
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1:23:39Reflect on our newly synchronous system
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1:24:45Set up to create interesting stateful circuits
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1:24:45Set up to create interesting stateful circuits
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1:24:45Set up to create interesting stateful circuits
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1:25:13Bit-serial multiplier
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1:25:13Bit-serial multiplier
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1:25:13Bit-serial multiplier
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1:26:35Spec out a bit-serial multiplier
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1:26:35Spec out a bit-serial multiplier
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1:26:35Spec out a bit-serial multiplier
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1:28:41Define Example39 as a bit-serial multiplier
1:28:41Define Example39 as a bit-serial multiplier
1:28:41Define Example39 as a bit-serial multiplier
1:31:41Check the graph of Example39
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1:31:41Check the graph of Example39
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1:31:41Check the graph of Example39
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1:32:06Create a simulation test of our bit-serial multiplier
1:32:06Create a simulation test of our bit-serial multiplier
1:32:06Create a simulation test of our bit-serial multiplier
1:35:51Simulate the bit-serial multiplier to see that it actually seems correct
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1:35:51Simulate the bit-serial multiplier to see that it actually seems correct
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1:35:51Simulate the bit-serial multiplier to see that it actually seems correct
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1:37:38Test our bit-serial multiplier
1:37:38Test our bit-serial multiplier
1:37:38Test our bit-serial multiplier
1:38:15Simulate the bit-serial multiplier and fail the test
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1:38:15Simulate the bit-serial multiplier and fail the test
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1:38:15Simulate the bit-serial multiplier and fail the test
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1:38:55Fix our bit-serial multiplier test
1:38:55Fix our bit-serial multiplier test
1:38:55Fix our bit-serial multiplier test
1:39:05Simulate the bit-serial multiplier, fail the test and investigate why
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1:39:05Simulate the bit-serial multiplier, fail the test and investigate why
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1:39:05Simulate the bit-serial multiplier, fail the test and investigate why
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1:44:05Try printing our product beside the result of Python's own multiplication AND'd with the mask
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1:44:05Try printing our product beside the result of Python's own multiplication AND'd with the mask
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1:44:05Try printing our product beside the result of Python's own multiplication AND'd with the mask
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1:45:49Make our bit-serial multiplier simulation perform one more iteration, to pass the test
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1:45:49Make our bit-serial multiplier simulation perform one more iteration, to pass the test
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1:45:49Make our bit-serial multiplier simulation perform one more iteration, to pass the test
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1:46:25Reflect on our bit-serial multipler
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1:46:25Reflect on our bit-serial multipler
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1:46:25Reflect on our bit-serial multipler
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1:46:58Create a faster version of our bit-serial multiplier using a p_valid_reg control signal
1:46:58Create a faster version of our bit-serial multiplier using a p_valid_reg control signal
1:46:58Create a faster version of our bit-serial multiplier using a p_valid_reg control signal
1:50:44Simulate our faster bit-serial multiplier, fail the test and investigate why
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1:50:44Simulate our faster bit-serial multiplier, fail the test and investigate why
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1:50:44Simulate our faster bit-serial multiplier, fail the test and investigate why
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1:51:17Change our bit-serial multiplier simulation not to check p_valid on the first iteration
1:51:17Change our bit-serial multiplier simulation not to check p_valid on the first iteration
1:51:17Change our bit-serial multiplier simulation not to check p_valid on the first iteration
1:52:06Simulate our faster bit-serial multiplier, fail the test again and continue to investigate why
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1:52:06Simulate our faster bit-serial multiplier, fail the test again and continue to investigate why
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1:52:06Simulate our faster bit-serial multiplier, fail the test again and continue to investigate why
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1:54:58Check out the outputs of our bit-serial multiplier instances
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1:54:58Check out the outputs of our bit-serial multiplier instances
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1:54:58Check out the outputs of our bit-serial multiplier instances
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1:55:37Rework our bit-serial multiplier simulation
1:55:37Rework our bit-serial multiplier simulation
1:55:37Rework our bit-serial multiplier simulation
1:57:34Simulate our faster bit-serial multiplier successfully
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1:57:34Simulate our faster bit-serial multiplier successfully
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1:57:34Simulate our faster bit-serial multiplier successfully
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1:58:07Spec out some test code we'd like our co-routine interface to allow
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1:58:07Spec out some test code we'd like our co-routine interface to allow
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1:58:07Spec out some test code we'd like our co-routine interface to allow
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2:00:00Introduce simulate_test()
2:00:00Introduce simulate_test()
2:00:00Introduce simulate_test()
2:03:06Introduce example39_test() to test our simulate_test()
2:03:06Introduce example39_test() to test our simulate_test()
2:03:06Introduce example39_test() to test our simulate_test()
2:05:11Run our simulate_test() successfully on example39_test()
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2:05:11Run our simulate_test() successfully on example39_test()
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2:05:11Run our simulate_test() successfully on example39_test()
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2:05:38Reflect on our co-routine interface
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2:05:38Reflect on our co-routine interface
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2:05:38Reflect on our co-routine interface
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2:07:20We are done for that, with a glimpse into the future of state machine composition
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2:07:20We are done for that, with a glimpse into the future of state machine composition
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2:07:20We are done for that, with a glimpse into the future of state machine composition
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Next: 'Sequential Logic, Part 2'
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