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Previous: 'Sequential Logic, Part 3'
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0:07Recap and set the stage for the day continuing with sequential logic
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0:07Recap and set the stage for the day continuing with sequential logic
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0:07Recap and set the stage for the day continuing with sequential logic
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0:42Review the off-stream bug-fix in the memory(), establishing read-after-write semantics
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0:42Review the off-stream bug-fix in the memory(), establishing read-after-write semantics
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0:42Review the off-stream bug-fix in the memory(), establishing read-after-write semantics
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3:05Review the off-stream bug-fix in fifo(), establishing registered output
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3:05Review the off-stream bug-fix in fifo(), establishing registered output
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3:05Review the off-stream bug-fix in fifo(), establishing registered output
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7:25Simulate our FIFO with the fifo_test_consumer() starting with idle cycles
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7:25Simulate our FIFO with the fifo_test_consumer() starting with idle cycles
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7:25Simulate our FIFO with the fifo_test_consumer() starting with idle cycles
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8:20Set up to cover a shift register-based FIFO implementation useful in Xilinx FPGAs
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8:20Set up to cover a shift register-based FIFO implementation useful in Xilinx FPGAs
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8:20Set up to cover a shift register-based FIFO implementation useful in Xilinx FPGAs
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10:10Shift register
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10:10Shift register
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10:10Shift register
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11:00Introduce shift_memory()
11:00Introduce shift_memory()
11:00Introduce shift_memory()
14:09Shifting sequential cells
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14:09Shifting sequential cells
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14:09Shifting sequential cells
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15:11Continue to implement shift_memory()
15:11Continue to implement shift_memory()
15:11Continue to implement shift_memory()
17:54Write a test of our shift memory
17:54Write a test of our shift memory
17:54Write a test of our shift memory
20:48Simulate our shift memory successfully
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20:48Simulate our shift memory successfully
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20:48Simulate our shift memory successfully
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21:46Establish read-after-write semantics in shift_memory()
21:46Establish read-after-write semantics in shift_memory()
21:46Establish read-after-write semantics in shift_memory()
23:09Simulate our shift memory successfully
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23:09Simulate our shift memory successfully
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23:09Simulate our shift memory successfully
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23:29Write a second test of our shift memory that reads in the first element before shifting in a new value
23:29Write a second test of our shift memory that reads in the first element before shifting in a new value
23:29Write a second test of our shift memory that reads in the first element before shifting in a new value
24:55Simulate our shift memory successfully
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24:55Simulate our shift memory successfully
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24:55Simulate our shift memory successfully
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25:05Shift register-based FIFO
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25:05Shift register-based FIFO
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25:05Shift register-based FIFO
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29:42Introduce shift_fifo(), renaming fifo() to ring_fifo()
29:42Introduce shift_fifo(), renaming fifo() to ring_fifo()
29:42Introduce shift_fifo(), renaming fifo() to ring_fifo()
38:47Test our shift FIFO
38:47Test our shift FIFO
38:47Test our shift FIFO
39:19Simulate our shift FIFO test and hit a TypeError, Inconsistent types
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39:19Simulate our shift FIFO test and hit a TypeError, Inconsistent types
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39:19Simulate our shift FIFO test and hit a TypeError, Inconsistent types
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39:32Make shift_fifo() explicitly compute the length
39:32Make shift_fifo() explicitly compute the length
39:32Make shift_fifo() explicitly compute the length
40:54Simulate our shift FIFO and step through to see what's taking it so long
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40:54Simulate our shift FIFO and step through to see what's taking it so long
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40:54Simulate our shift FIFO and step through to see what's taking it so long
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45:00Fix the length computation in shift_fifo()
45:00Fix the length computation in shift_fifo()
45:00Fix the length computation in shift_fifo()
45:57Simulate our shift FIFO successfully
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45:57Simulate our shift FIFO successfully
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45:57Simulate our shift FIFO successfully
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46:20Start fifo_test_consumer() with 100 idle cycles
46:20Start fifo_test_consumer() with 100 idle cycles
46:20Start fifo_test_consumer() with 100 idle cycles
46:24Simulate our shift FIFO with the fifo_test_consumer() starting with idle cycles
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46:24Simulate our shift FIFO with the fifo_test_consumer() starting with idle cycles
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46:24Simulate our shift FIFO with the fifo_test_consumer() starting with idle cycles
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46:46Prevent shift_fifo() from filling up completely
46:46Prevent shift_fifo() from filling up completely
46:46Prevent shift_fifo() from filling up completely
47:07Simulate our shift FIFO successfully
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47:07Simulate our shift FIFO successfully
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47:07Simulate our shift FIFO successfully
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47:50Establish registered outputs in shift_fifo()
47:50Establish registered outputs in shift_fifo()
47:50Establish registered outputs in shift_fifo()
48:13Simulate our shift FIFO with registered outputs successfully
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48:13Simulate our shift FIFO with registered outputs successfully
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48:13Simulate our shift FIFO with registered outputs successfully
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49:21Block RAM in Xilinx FPGAs1
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49:21Block RAM in Xilinx FPGAs1
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49:21Block RAM in Xilinx FPGAs1
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51:00The basic logic building block in Xilinx: a 6-input 1-output bit lookup table2
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51:00The basic logic building block in Xilinx: a 6-input 1-output bit lookup table2
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51:00The basic logic building block in Xilinx: a 6-input 1-output bit lookup table2
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54:37The downside of building large FIFOs with shift registers
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54:37The downside of building large FIFOs with shift registers
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54:37The downside of building large FIFOs with shift registers
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56:41Valid / ready signaling3
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56:41Valid / ready signaling3
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56:41Valid / ready signaling3
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1:02:57Introduce chain_fifo()
1:02:57Introduce chain_fifo()
1:02:57Introduce chain_fifo()
1:10:23Write a test of our chain FIFO
1:10:23Write a test of our chain FIFO
1:10:23Write a test of our chain FIFO
1:13:17Simulate our chain FIFO to find that it is successfully enqueueing, but slow
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1:13:17Simulate our chain FIFO to find that it is successfully enqueueing, but slow
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1:13:17Simulate our chain FIFO to find that it is successfully enqueueing, but slow
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1:14:55Simulate it from the command line, hopefully for speed
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1:14:55Simulate it from the command line, hopefully for speed
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1:14:55Simulate it from the command line, hopefully for speed
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1:17:19Simulate it with smaller FIFOs
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1:17:19Simulate it with smaller FIFOs
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1:17:19Simulate it with smaller FIFOs
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1:18:28Investigate why the chain_fifo() isn't getting the message that the producer has finished
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1:18:28Investigate why the chain_fifo() isn't getting the message that the producer has finished
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1:18:28Investigate why the chain_fifo() isn't getting the message that the producer has finished
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1:19:30Fix chain_fifo() to correctly dequeue
1:19:30Fix chain_fifo() to correctly dequeue
1:19:30Fix chain_fifo() to correctly dequeue
1:22:31Simulate the size 2 chain FIFO and watch what it does
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1:22:31Simulate the size 2 chain FIFO and watch what it does
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1:22:31Simulate the size 2 chain FIFO and watch what it does
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1:24:31Simulate a size 3 chain FIFO, also successfully
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1:24:31Simulate a size 3 chain FIFO, also successfully
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1:24:31Simulate a size 3 chain FIFO, also successfully
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1:24:46Simulate a size 4 chain FIFO, unsuccessfully, and step through chain_fifo()
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1:24:46Simulate a size 4 chain FIFO, unsuccessfully, and step through chain_fifo()
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1:24:46Simulate a size 4 chain FIFO, unsuccessfully, and step through chain_fifo()
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1:27:33Check the graph of a size 4 chain FIFO
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1:27:33Check the graph of a size 4 chain FIFO
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1:27:33Check the graph of a size 4 chain FIFO
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1:30:11Investigate the possibility that we have a latent delay-related bug
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1:30:11Investigate the possibility that we have a latent delay-related bug
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1:30:11Investigate the possibility that we have a latent delay-related bug
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1:34:32Scrutinise the graph of a size 4 chain FIFO
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1:34:32Scrutinise the graph of a size 4 chain FIFO
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1:34:32Scrutinise the graph of a size 4 chain FIFO
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1:35:33Scrutinise the code of chain_fifo()
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1:35:33Scrutinise the code of chain_fifo()
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1:35:33Scrutinise the code of chain_fifo()
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1:37:08Call it a day, with another recommendation of UC Berkeley's 'Interfaces: "FIFO" (a.k.a. Ready/Valid)'4 and a glimpse into the future
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1:37:08Call it a day, with another recommendation of UC Berkeley's 'Interfaces: "FIFO" (a.k.a. Ready/Valid)'4 and a glimpse into the future
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1:37:08Call it a day, with another recommendation of UC Berkeley's 'Interfaces: "FIFO" (a.k.a. Ready/Valid)'4 and a glimpse into the future
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