RISC-V Toolchain Implementation
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0:09Recap and set the stage for the day, with a note that off-stream work will now be covered in write-ups, rather than on stream
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0:09Recap and set the stage for the day, with a note that off-stream work will now be covered in write-ups, rather than on stream
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0:09Recap and set the stage for the day, with a note that off-stream work will now be covered in write-ups, rather than on stream
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2:05Plan to create two tools: assembler and simulator
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2:05Plan to create two tools: assembler and simulator
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2:05Plan to create two tools: assembler and simulator
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5:44Chapter 19 - RV32/64G Instruction Set Listings1
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5:44Chapter 19 - RV32/64G Instruction Set Listings1
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5:44Chapter 19 - RV32/64G Instruction Set Listings1
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8:05Dive into writing our RISC-V assembler, starting with an Instruction struct2
8:05Dive into writing our RISC-V assembler, starting with an Instruction struct2
8:05Dive into writing our RISC-V assembler, starting with an Instruction struct2
13:30Introduce decode_instruction() and encode_instruction() and declare our immediate field masks3
13:30Introduce decode_instruction() and encode_instruction() and declare our immediate field masks3
13:30Introduce decode_instruction() and encode_instruction() and declare our immediate field masks3
20:47Add cases for LUI, AUIPC, JAL, JALR and the branch instructions in decode_instruction()4
20:47Add cases for LUI, AUIPC, JAL, JALR and the branch instructions in decode_instruction()4
20:47Add cases for LUI, AUIPC, JAL, JALR and the branch instructions in decode_instruction()4
35:45Introduce empty decode_u_instruction(), decode_j_instruction(), decode_b_instruction() and decode_i_instruction()
35:45Introduce empty decode_u_instruction(), decode_j_instruction(), decode_b_instruction() and decode_i_instruction()
35:45Introduce empty decode_u_instruction(), decode_j_instruction(), decode_b_instruction() and decode_i_instruction()
36:21Look into handling the "'riscv_Op': undeclared identifier" error
36:21Look into handling the "'riscv_Op': undeclared identifier" error
36:21Look into handling the "'riscv_Op': undeclared identifier" error
38:54Just disable typeinfo for now
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38:54Just disable typeinfo for now
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38:54Just disable typeinfo for now
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39:36Add cases for the load and store instructions in decode_instruction(), also introducing an empty decode_s_instruction()5
39:36Add cases for the load and store instructions in decode_instruction(), also introducing an empty decode_s_instruction()5
39:36Add cases for the load and store instructions in decode_instruction(), also introducing an empty decode_s_instruction()5
44:27Add a case for the integer register-immediate instructions in decode_instruction()6
44:27Add a case for the integer register-immediate instructions in decode_instruction()6
44:27Add a case for the integer register-immediate instructions in decode_instruction()6
58:57Add a case for the FENCE / FENCE.I instructions in decode_instruction()7
58:57Add a case for the FENCE / FENCE.I instructions in decode_instruction()7
58:57Add a case for the FENCE / FENCE.I instructions in decode_instruction()7
1:00:38Enable Ion's scan_int() to skip _ delimiters in int declarations
1:00:38Enable Ion's scan_int() to skip _ delimiters in int declarations
1:00:38Enable Ion's scan_int() to skip _ delimiters in int declarations
1:03:26Finish up the FENCE / FENCE.I case in decode_instruction()8
1:03:26Finish up the FENCE / FENCE.I case in decode_instruction()8
1:03:26Finish up the FENCE / FENCE.I case in decode_instruction()8
1:09:00Add a case for the integer register-register instructions in decode_instruction()9
1:09:00Add a case for the integer register-register instructions in decode_instruction()9
1:09:00Add a case for the integer register-register instructions in decode_instruction()9
1:18:27Add a case for the environment call and breakpoints instructions ECALL and EBREAK in decode_instruction()10
1:18:27Add a case for the environment call and breakpoints instructions ECALL and EBREAK in decode_instruction()10
1:18:27Add a case for the environment call and breakpoints instructions ECALL and EBREAK in decode_instruction()10
1:22:25Include the CSR (Control and Status Register) instructions in the ECALL / EBREAK case in decode_instruction(), introducing decode_csr_instruction()11
1:22:25Include the CSR (Control and Status Register) instructions in the ECALL / EBREAK case in decode_instruction(), introducing decode_csr_instruction()11
1:22:25Include the CSR (Control and Status Register) instructions in the ECALL / EBREAK case in decode_instruction(), introducing decode_csr_instruction()11
1:25:35Reflect on the day's work
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1:25:35Reflect on the day's work
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1:25:35Reflect on the day's work
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1:26:55Q&A
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1:26:55Q&A
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1:26:55Q&A
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1:28:03arbitraryslayer Hi pervognsen, I have a quick question. Why do you think C is preferred over C++ for system level when C++ has more features than C?
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1:28:03arbitraryslayer Hi pervognsen, I have a quick question. Why do you think C is preferred over C++ for system level when C++ has more features than C?
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1:28:03arbitraryslayer Hi pervognsen, I have a quick question. Why do you think C is preferred over C++ for system level when C++ has more features than C?
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1:29:11nothings2 Also I wonder if bitfields would make instruction decoding cleaner
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1:29:11nothings2 Also I wonder if bitfields would make instruction decoding cleaner
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1:29:11nothings2 Also I wonder if bitfields would make instruction decoding cleaner
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1:29:51Cut over to the extra stream
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1:29:51Cut over to the extra stream
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1:29:51Cut over to the extra stream
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