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Bitwise»Episode Guide
Sequential Logic, Part 3
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Per Vognsen
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Matt Mascarenhas
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0:07Recap and set the stage for the day covering memory
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0:07Recap and set the stage for the day covering memory
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0:07Recap and set the stage for the day covering memory
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1:21sharlock93 Is the timing different now?
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1:21sharlock93 Is the timing different now?
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1:21sharlock93 Is the timing different now?
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1:47Synthesising memory out of registers, muxers and decoders
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1:47Synthesising memory out of registers, muxers and decoders
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1:47Synthesising memory out of registers, muxers and decoders
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2:42Introduce memory()
2:42Introduce memory()
2:42Introduce memory()
5:03Introduce ispow2()
5:03Introduce ispow2()
5:03Introduce ispow2()
5:34Continue to implement memory()
5:34Continue to implement memory()
5:34Continue to implement memory()
7:16Introduce a generalised recursive mux()
7:16Introduce a generalised recursive mux()
7:16Introduce a generalised recursive mux()
9:37Implement a read port in memory(), noting that it is a combinational or asynchronous read port
9:37Implement a read port in memory(), noting that it is a combinational or asynchronous read port
9:37Implement a read port in memory(), noting that it is a combinational or asynchronous read port
10:42Fix module() decoration of functions
10:42Fix module() decoration of functions
10:42Fix module() decoration of functions
14:18Try and instantiate some memory, fixing a typo in mux()
14:18Try and instantiate some memory, fixing a typo in mux()
14:18Try and instantiate some memory, fixing a typo in mux()
14:44Inspect our memory in the debugger
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14:44Inspect our memory in the debugger
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14:44Inspect our memory in the debugger
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15:19Implement a write port in memory()
15:19Implement a write port in memory()
15:19Implement a write port in memory()
18:10Decoding an 8-bit binary address to an array of 256 bit signals
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18:10Decoding an 8-bit binary address to an array of 256 bit signals
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18:10Decoding an 8-bit binary address to an array of 256 bit signals
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20:02Finish implementing a write port in memory()
20:02Finish implementing a write port in memory()
20:02Finish implementing a write port in memory()
21:19Introduce example43_test() as a simple memory test
21:19Introduce example43_test() as a simple memory test
21:19Introduce example43_test() as a simple memory test
24:10Run simulate_test() successfully on example43_test
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24:10Run simulate_test() successfully on example43_test
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24:10Run simulate_test() successfully on example43_test
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24:14Augment example43_test() with a scramble() function
24:14Augment example43_test() with a scramble() function
24:14Augment example43_test() with a scramble() function
26:56Run simulate_test() unsuccessfully on example43_test
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26:56Run simulate_test() unsuccessfully on example43_test
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26:56Run simulate_test() unsuccessfully on example43_test
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27:18Fix example43_test() to set the write_enable
27:18Fix example43_test() to set the write_enable
27:18Fix example43_test() to set the write_enable
27:48Run simulate_test() successfully on example43_test, and step through it to prove it
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27:48Run simulate_test() successfully on example43_test, and step through it to prove it
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27:48Run simulate_test() successfully on example43_test, and step through it to prove it
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28:22Adding more read / write memory ports, using a one-hot mux
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28:22Adding more read / write memory ports, using a one-hot mux
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28:22Adding more read / write memory ports, using a one-hot mux
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31:26Rename memory() to register_memory() and set up to create a builtin memory primitive
31:26Rename memory() to register_memory() and set up to create a builtin memory primitive
31:26Rename memory() to register_memory() and set up to create a builtin memory primitive
33:50Introduce a new memory() and Memory class as a builtin primitive
33:50Introduce a new memory() and Memory class as a builtin primitive
33:50Introduce a new memory() and Memory class as a builtin primitive
38:09See if someone's at the door
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38:09See if someone's at the door
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38:09See if someone's at the door
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38:41Return
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38:41Return
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38:41Return
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38:56Define MemoryReadPort class
38:56Define MemoryReadPort class
38:56Define MemoryReadPort class
44:53Remove MemoryReadPort in favour of having only one read and write port by default
44:53Remove MemoryReadPort in favour of having only one read and write port by default
44:53Remove MemoryReadPort in favour of having only one read and write port by default
48:53Create Example43 as a memory module
48:53Create Example43 as a memory module
48:53Create Example43 as a memory module
51:21Run it to determine that it at least type-checked
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51:21Run it to determine that it at least type-checked
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51:21Run it to determine that it at least type-checked
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52:06Check the graph of our memory module
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52:06Check the graph of our memory module
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52:06Check the graph of our memory module
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52:29Try to compile our Example43 memory module
52:29Try to compile our Example43 memory module
52:29Try to compile our Example43 memory module
52:41Simulate Example43 to see that it does explode
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52:41Simulate Example43 to see that it does explode
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52:41Simulate Example43 to see that it does explode
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53:02Consider how to enable linearize() to handle unconnected output nodes
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53:02Consider how to enable linearize() to handle unconnected output nodes
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53:02Consider how to enable linearize() to handle unconnected output nodes
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55:34Enable linearize() to handle abstract modules that cannot get inlined, defining a dummy GenericMemory class
55:34Enable linearize() to handle abstract modules that cannot get inlined, defining a dummy GenericMemory class
55:34Enable linearize() to handle abstract modules that cannot get inlined, defining a dummy GenericMemory class
58:26Run it to find that it fails on the memory module and investigate why
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58:26Run it to find that it fails on the memory module and investigate why
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58:26Run it to find that it fails on the memory module and investigate why
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1:02:05Revert our builtin memory primitive code and use our model memory for the rest of the stream
1:02:05Revert our builtin memory primitive code and use our model memory for the rest of the stream
1:02:05Revert our builtin memory primitive code and use our model memory for the rest of the stream
1:04:06Run it to see that it seems to work
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1:04:06Run it to see that it seems to work
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1:04:06Run it to see that it seems to work
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1:04:16FIFO (first-in, first-out
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1:04:16FIFO (first-in, first-out
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1:04:16FIFO (first-in, first-out
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1:05:31Introduce fifo() module
1:05:31Introduce fifo() module
1:05:31Introduce fifo() module
1:15:31Write a test of our fifo module with a producer and consumer
1:15:31Write a test of our fifo module with a producer and consumer
1:15:31Write a test of our fifo module with a producer and consumer
1:21:13Run our fifo test, unsuccessfully
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1:21:13Run our fifo test, unsuccessfully
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1:21:13Run our fifo test, unsuccessfully
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1:21:42Make fifo() set the dequeue_data to output(mem.read_data)
1:21:42Make fifo() set the dequeue_data to output(mem.read_data)
1:21:42Make fifo() set the dequeue_data to output(mem.read_data)
1:22:15Simulate our fifo, fail the test and investigate why
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1:22:15Simulate our fifo, fail the test and investigate why
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1:22:15Simulate our fifo, fail the test and investigate why
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1:23:26Respecify "empty" and "full" in fifo() as their inverse, and make fifo_test_producer() and fifo_test_consumer() yield
1:23:26Respecify "empty" and "full" in fifo() as their inverse, and make fifo_test_producer() and fifo_test_consumer() yield
1:23:26Respecify "empty" and "full" in fifo() as their inverse, and make fifo_test_producer() and fifo_test_consumer() yield
1:24:40Step through our fifo test to determine that dequeue_data is incorrectly set on the second round
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1:24:40Step through our fifo test to determine that dequeue_data is incorrectly set on the second round
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1:24:40Step through our fifo test to determine that dequeue_data is incorrectly set on the second round
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1:25:53Try to enable fifo() to keep the queue readiness and reading in phase by delaying the output
1:25:53Try to enable fifo() to keep the queue readiness and reading in phase by delaying the output
1:25:53Try to enable fifo() to keep the queue readiness and reading in phase by delaying the output
1:28:15Simulate our fifo, fail the test again and continue to investigate why
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1:28:15Simulate our fifo, fail the test again and continue to investigate why
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1:28:15Simulate our fifo, fail the test again and continue to investigate why
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1:29:32Try to enable fifo() to keep everything in phase by also reading from the next address
1:29:32Try to enable fifo() to keep everything in phase by also reading from the next address
1:29:32Try to enable fifo() to keep everything in phase by also reading from the next address
1:31:29Change our fifo test to enqueue values starting from 1
1:31:29Change our fifo test to enqueue values starting from 1
1:31:29Change our fifo test to enqueue values starting from 1
1:31:54Simulate our fifo to see that it all worked, but failed the test
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1:31:54Simulate our fifo to see that it all worked, but failed the test
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1:31:54Simulate our fifo to see that it all worked, but failed the test
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1:32:11Change our fifo test assertion to mask the test value, and then switch it all back to enqueuing values starting from 0
1:32:11Change our fifo test assertion to mask the test value, and then switch it all back to enqueuing values starting from 0
1:32:11Change our fifo test assertion to mask the test value, and then switch it all back to enqueuing values starting from 0
1:32:49Simulate our fifo successfully
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1:32:49Simulate our fifo successfully
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1:32:49Simulate our fifo successfully
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1:33:03Understanding how fifo() keeps everything in phase
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1:33:03Understanding how fifo() keeps everything in phase
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1:33:03Understanding how fifo() keeps everything in phase
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1:36:48Call it a day with some final thoughts on our FIFO memory and a glimpse into the future
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1:36:48Call it a day with some final thoughts on our FIFO memory and a glimpse into the future
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1:36:48Call it a day with some final thoughts on our FIFO memory and a glimpse into the future
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