After watching the first two streams on DSL and circuit simulation, I've got a few questions that are related:
What are the plans for memory cells? Are they going to be abstracted into a type of Node or are they going to be built out of Nodes that are currently available?
Are cycles going to be simulated, or are we sticking to circuits without cycles?
Edited by agnar
on
Generally it would be nice to have plans.
At least similar to
https://github.com/pervognsen/bit...ob/master/notes/ion_motivation.md
or even better - precise formal specification of the language . "Run and pray it works as you think it works " seems counterintuitive when it comes to hardware
At least similar to
https://github.com/pervognsen/bit...ob/master/notes/ion_motivation.md
or even better - precise formal specification of the language . "Run and pray it works as you think it works " seems counterintuitive when it comes to hardware
Those first few streams weren't intended to be anything other than Python/DSL warm-up. I tried to make that clear, but I'll try to emphasize that more.
To answer your questions:
Registers and memories in general will be abstracted into black box modules with the appropriate multi-cycle behavior. It won't be like Verilog or VHDL which has imperative simulation semantics at its core.
It depends on what you mean by cycles. To build a state machine you need the next state to depend on the current state, but there isn't a true combinational loop because the apparent cycle is broken by flips flops or other memory elements. Combinational loops corresponding to logic equations like x = ~~~x (a ring oscillator) will be expressible in the circuit language (although not the toy subset that was demonstrated in the first two streams) but won't be simulated (it requires event-driven simulation) and we won't be needing anything like that for synthesis anyway.
For the next couple of streams expect to still see some bottom-up exploration before I cover the longer-term plans.
To answer your questions:
Registers and memories in general will be abstracted into black box modules with the appropriate multi-cycle behavior. It won't be like Verilog or VHDL which has imperative simulation semantics at its core.
It depends on what you mean by cycles. To build a state machine you need the next state to depend on the current state, but there isn't a true combinational loop because the apparent cycle is broken by flips flops or other memory elements. Combinational loops corresponding to logic equations like x = ~~~x (a ring oscillator) will be expressible in the circuit language (although not the toy subset that was demonstrated in the first two streams) but won't be simulated (it requires event-driven simulation) and we won't be needing anything like that for synthesis anyway.
For the next couple of streams expect to still see some bottom-up exploration before I cover the longer-term plans.